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3-8 yrs. Bengaluru/Bangalore, Hubli

Job Description Primary and hands on experience in Analog and IO Circuit Desig

Job Description

Primary and hands on experience in Analog and IO Circuit Design
1) Proven Track record with Silicon proven circuit Design in : Amplifiers , Bias generators , Bandgap , IO
Transmitter and receiver
2) Technology Exposure : 7nm,16nm and Bulk process like 28nm and 40nm
3) Well versed with Liberty , IBIS , Verilog View generation
4) Can understand and Review block layout and Define Constraint
5) Manage project independent execution

Job Requirements

Bachelors / Master Degree in E&E and E&C
Experience : 4 to 14 years
Strong communication and team work skills
Job Location : Bangalore / Hubli / Kolkata
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2-7 yrs. Bengaluru/Bangalore

Practice: Sankalp memory practice deals in memory compiler or instance developm
Practice:

Sankalp memory practice deals in memory compiler or instance development from specification to gds.
Team with strong experience in development of low power, high performance, high density SRAM
memories for 5nm to 180nm technology nodes. Team also has experience in developing flash memories.
The project are done in T&M (time and material) or ownership/turnkey mode. The practice serves many
leading MNCs involved in memory IP development.

Job Description

Independent work execution
Experience working with circuit designers
Good experience in leaf cell/block level layouts
Good experience in memory compiler layouts
Good understanding and hands on experience using verification tools (Calibre) for
LVS and DRC
Experience in handling IR/EM related issues in memory layouts.
Awareness of second order effects
Experience of working in 16nm / 14nm / 10nm/ 7nm/ Finfet technology node is
preferred
Good communication skills and a team player

Job Requirements

Bachelors / Master Degree in E&E and E&C
Experience : 2 to 7 years
Strong communication and team work skills
Job Location : Bangalore / Noida
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2-7 yrs. Bengaluru/Bangalore

Sankalp Semiconductor offers an integrated portfolio of services and solutions


Sankalp Semiconductor offers an integrated portfolio of services and solutions to its customers in key semiconductor domains including analog & mixed signal, digital, high-speed physical interface IP, Embedded Memory Compiler, IOs and EDA modelling. Sankalp Semiconductor is a preferred semiconductor design service partners to multiple Fortune 500 companies in the Automotive, Consumer, Networking, Wireless, IoT, Medical electronics and Foundry space. The company enables its customers to achieve their time-to-market window by delivering first pass silicon designs and engage with product engineering teams across the globe to design System on- Chip. Sankalp Semiconductor is based in Sunnyvale, California, with offices in USA, India, Canada, Germany and Malaysia. www.sankalpsemi.com

Practice:

Sankalp memory practice deals in memory compiler or instance development from specification to gds. Team with strong experience in development of low power, high performance, high density SRAM memories for 5nm to 180nm technology nodes. Team also has experience in developing flash memories. The project are done in T&M (time and material) or ownership/turnkey mode. The practice serves many leading MNCs involved in memory IP development.

Standard Cell Design

Job Description

Development of the standard cell library from scratch and support of existing libraries.
Circuit design: PPA tradeoff between different cell circuit architecture.
Experience in the field of Standard cell design, characterization, modelling and QA.
Design experience with deep sub-micron process
Should be well versed with standard EDA tools used for RC-extraction, SPICE simulators and schematic/layout editors.
Good Understanding of the views like lef, NLDM, CCS libs etc..
Understanding issues related to advanced nanometer technologies, IR, electro migration, SI, LOD, Proximity-effects etc..
Good automation skill using perl, tcl.
Good debugging and problem solving skills.
.
Job Requirements
Bachelors / Master Degree in E&E and E&C
Experience : 2 to 7 years
Strong communication and team work skills
Job Location : Bangalore

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3-8 yrs. Bengaluru/Bangalore

Job Description Development of the standard cell library from scratch and suppo
Job Description

Development of the standard cell library from scratch and support of existing libraries.
1. Circuit design: PPA trade-off between different cell circuit architecture.
2. Experience in the field of Standard cell Layout design.
3. Design experience with deep sub-micron process & Fin FET
4. Should be well versed with standard EDA tools used for layout editors /RC-extraction, SPICE
simulators and schematic
5. Good Understanding of the views like lef.
6. Understanding issues related to advanced nanometer technologies, IR, electro migration, SI,
LOD, Proximity-effects etc..
7. Good automation skill using perl, tcl.
8. Good debugging and problem solving skills.

Job Requirements

1. Bachelors / Master Degree in E&E and E&C
2. Experience : 2 to 8 years
3. Strong communication and team work skills
4. Job Location : Bangalore
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3-8 yrs. Bengaluru/Bangalore, Kolkata, Hubli

Sankalp Semiconductor offers an integrated portfolio of services and solutions
Sankalp Semiconductor offers an integrated portfolio of services and solutions to its customers in key semiconductor domains including analog & mixed signal, digital, high-speed physical interface IP, Embedded Memory Compiler, IOs and EDA modelling.

Sankalp Semiconductor is a preferred semiconductor design service partners to multiple Fortune 500 companies in the Automotive, Consumer, Networking, Wireless, IoT, Medical electronics and Foundry space. The company enables its customers to achieve their time-to-market window by delivering first pass silicon designs and engage with product engineering teams across the globe to design System on- Chip.

Sankalp Semiconductor is based in Sunnyvale, California, with offices in USA, India, Canada, Germany and Malaysia. www.sankalpsemi.com


Practice:
Project involves the layout-design of various challenging Analog & Mixed-Signal modules like PLL, Data-Converters & Power-Management blocks, in cutting-edge technologies.
Qualification/Experience/Skills Required
Candidate must possess a minimum of Bachelor Degree in Electrical/Electronic Manufacturing Information Technology and Services/Computer Software.


3-6 years of experience in AMS/RF layout-design
Good Understanding of CMOS Fundamentals, IC-Fabrication & Circuit-basics
Good Understanding of Layout-Flow & various Reliability Issues
Preferred experience in modules like PLL, Data-Converters & PMIC blocks
Good exposure to EDA tools like Virtuoso LE/XL, Assura, PVS, Calibre
Preferred experience in Deep Sub-Micron/Finfet / Bi-CMOS technologies
Roles & Responsibilities
Independently execute layout-design of the assigned Analog & Mixed-Signal / RF blocks either at Onsite or Off-shore, which includes floor-planning as per area & top-level, parasitic-aware routing & doing various required physical verifications.
Responsible for the on-time delivery of block-level layouts, with acceptable quality
Co-ordinate effectively with the customer & team-members, for the successful overall project execution
Guide junior team-members in their execution of block-level layouts & review their work
Contribute to effective project-management.
Job Location: Bangalore, Hubballi, Kolkata
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3-8 yrs. Bengaluru/Bangalore

Practice: Sankalp memory practice deals in memory compiler or instance developm
Practice:

Sankalp memory practice deals in memory compiler or instance development from specification to gds.
Team with strong experience in development of low power, high performance, high density SRAM
memories for 5nm to 180nm technology nodes. Team also has experience in developing flash memories.
The project are done in T&M (time and material) or ownership/turnkey mode. The practice serves many
leading MNCs involved in memory IP development.


Job Description

Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis and Monte
Carlo Simulations.
Exposure to full embedded memory design flow: Architecture, circuit design, physical
implementation, compiler automation, characterization, timing and model generation.
Good experience in design verification: Sense amplifier analysis, self-time analysis and
marginality analysis.
Good exposure to validation of the characterized data.
Strong knowledge of physical implementation impact on circuit performance.
Experience with the most advanced technology nodes up to 28nm and below.

Job Requirements

Bachelors / Master Degree in E&E and E&C
Experience : 3 to 9 years
Strong communication and team work skills
Job Location : Bangalore / Noida
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10-20 yrs. Delhi/NCR, Bengaluru/Bangalore

Practice: Sankalp memory practice deals in memory compiler or instance developm
Practice:

Sankalp memory practice deals in memory compiler or instance development from specification to gds.
Team with strong experience in development of low power, high performance, high density SRAM
memories for 5nm to 180nm technology nodes. Team also has experience in developing flash memories.
The project are done in T&M (time and material) or ownership/turnkey mode. The practice serves many
leading MNCs involved in memory IP development.


Job Description

Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis and Monte
Carlo Simulations.
Exposure to full embedded memory design flow: Architecture, circuit design, physical
implementation, compiler automation, characterization, timing and model generation.
Good experience in design verification: Sense amplifier analysis, self-time analysis and
marginality analysis.
Good exposure to validation of the characterized data.
Strong knowledge of physical implementation impact on circuit performance.
Experience with the most advanced technology nodes up to 28nm and below.

Job Requirements

Bachelors / Master Degree in E&E and E&C
Experience : 10 to 20 years
Strong communication and team work skills
Job Location : Bangalore / Noida
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3-8 yrs. Bengaluru/Bangalore

Design For Test experience, Scan insertion, ATPG (Test Pattern Generation). Awa
Design For Test experience, Scan insertion, ATPG (Test Pattern Generation).

Awareness of MemBIST flow.

Familiarity with ATE, automatic test equipment.

Work experience in deep sub-micron technologies like 45nm and below.

EDA Tools Synopsys, Mentor Graphics (Flextest/fastscan), Atrenta, etc.

Scripting knowledge on perl. SKILL.

Understanding the overall design, preparing a test plan, doing scan insertion,

memory test collar development using tools like MEMBIST, functional pattern generation and verification on design, etc.

Need to be able to discuss with RTL or custom designers and align on test methodology, debug test issues and suggest improvements to test methodology.

Need to be able to train and groom a set of junior engineers in the area of DFT.
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4-9 yrs. Bengaluru/Bangalore, Ahmedabad

Practice: RTL Design practice is responsible for that part of the ASIC design f
Practice:

RTL Design practice is responsible for that part of the ASIC design flow from Specification/Requirements
to RTL. The primary offering of this practice includes Architecture definition, IP/Sub-system Design, SoC
Integration, Test chip Design. This practice also does Digital design for Analog that includes Digital
controllers for PHYs and works on Analog on Top designs. RTL Design team also has FPGA design
capabilities including ASIC conversion and FPGA prototyping using Xilinx/Actel FPGAs. The team ensures
quality RTL reducing the iterations of verification and physical implementation thereby enabling lesser
time to market.

Job Description

Hands-on in Verilog/VHDL
Hands on in Linting, Clock Domain Crossing (CDC) checks, equivalence checks
Experience in Digital module micro-architecture and design
Experience in basic RTL simulation
Good knowledge of Synthesis, STA and DFT aware design
Hands-on in Perl/Unix scripting
Hands on in SoC level RTL integration
Excellent analytical, and problem solving skills
Self-motivated, assertive, positive attitude, excellent communication skills and ability to excel in
a team environment.
Be able to work with teams at remote locations with different time zone.
Be motivated to continuously develop skills and accept a variety of responsibilities as part of
contributing to the project's success

Roles & Responsibilities

Perform Microarchitecture and detailed block design from system requirements/specifications
Perform RTL coding, Lint checks, CDC checks, SDC creation, equivalency checking, STA result
review, RTL/gate level simulations debugging
Creating timing constraint file
Working closely with synthesis, STA, PD and DFT teams to meet all functional requirements,
performance, power and area goals
Technical interaction with customers and support team
Guiding a team of junior engineers

Job Requirements

Bachelors / Master Degree in E&E and E&C
Experience : 4 to 9 years
Strong communication and team work skills
Job Location : Bangalore / Ahmedabad
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8-12 yrs. Bengaluru/Bangalore, Ahmedabad

Practice Physical Design team is working on block/top level physical design

Practice

Physical Design team is working on block/top level physical design tasks including synthesis, Place & route,
STA, EM/IR checks and physical verification. We serve the Tier 1 customers in the semiconductor space.
Candidate is expected to have expertise in either Cadence or Synopsys flows and should be capable of
executing block or full chip level tasks independently.


Job Description
* Hands on experience on the entire PD Flow from Netlist to GDSII
(Floorplanning, Power Planning, Placement & Optimization, CTS, Routing, ECO, STA)
* Working knowledge about OCV, MM/MC optimization and multi power designs (Level shifters,
Isolation cells etc)
* Exposure STA in designs that have Crosstalk delay OR noise /EM
* Strong in areas on CTS and skew fixing
* Library preparation in any environment (Synopsys, Cadence etc)
* Working knowledge on Physical verifications tasks at lower nodes (data base
merging / DRC / LVS / ERC  / PERC / Antenna /ESD/LUP analysis/fixing ) at block level/chip level
* Job would require complete ownership from netlist to GDS for blocks at Block level OR full chip level
* Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage

Job Requirements
Bachelors / Master Degree in E&E and E&C
Experience : 8 to 12 years
Strong communication and team work skills
Job Location : Bangalore / Ahmedabad
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2-7 yrs. Delhi/NCR, Bengaluru/Bangalore

Practice: Sankalp memory practice deals in memory compiler or instance developm
Practice:

Sankalp memory practice deals in memory compiler or instance development from specification to gds.
Team with strong experience in development of low power, high performance, high density SRAM
memories for 5nm to 180nm technology nodes. Team also has experience in developing flash memories.
The project are done in T&M (time and material) or ownership/turnkey mode. The practice serves many
leading MNCs involved in memory IP development.


Job Description

Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis and Monte
Carlo Simulations.
Exposure to full embedded memory design flow: Architecture, circuit design, physical
implementation, compiler automation, characterization, timing and model generation.
Good experience in design verification: Sense amplifier analysis, self-time analysis and
marginality analysis.
Good exposure to validation of the characterized data.
Strong knowledge of physical implementation impact on circuit performance.
Experience with the most advanced technology nodes up to 28nm and below.

Job Requirements

Bachelors / Master Degree in E&E and E&C
Experience : 2 to 7 years
Strong communication and team work skills
Job Location : Bangalore / Noida
... More
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4-9 yrs. Bengaluru/Bangalore, Ahmedabad

Practice Physical Design team is working on block/top level physical design

Practice

Physical Design team is working on block/top level physical design tasks including synthesis, Place & route,
STA, EM/IR checks and physical verification. We serve the Tier 1 customers in the semiconductor space.
Candidate is expected to have expertise in either Cadence or Synopsys flows and should be capable of
executing block or full chip level tasks independently.


Job Description
* Hands on experience on the entire PD Flow from Netlist to GDSII
(Floorplanning, Power Planning, Placement & Optimization, CTS, Routing, ECO, STA)
* Working knowledge about OCV, MM/MC optimization and multi power designs (Level shifters,
Isolation cells etc)
* Exposure STA in designs that have Crosstalk delay OR noise /EM
* Strong in areas on CTS and skew fixing
* Library preparation in any environment (Synopsys, Cadence etc)
* Working knowledge on Physical verifications tasks at lower nodes (data base
merging / DRC / LVS / ERC  / PERC / Antenna /ESD/LUP analysis/fixing ) at block level/chip level
* Job would require complete ownership from netlist to GDS for blocks at Block level OR full chip level
* Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage

Job Requirements
Bachelors / Master Degree in E&E and E&C
Experience : 4 to 9 years
Strong communication and team work skills
Job Location : Bangalore / Ahmedabad
... More
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2-7 yrs. Bengaluru/Bangalore

Sankalp Semiconductor offers an integrated portfolio of services and solutions


Sankalp Semiconductor offers an integrated portfolio of services and solutions to its customers in key semiconductor domains including analog & mixed signal, digital, high-speed physical interface IP, Embedded Memory Compiler, IOs and EDA modelling. Sankalp Semiconductor is a preferred semiconductor design service partners to multiple Fortune 500 companies in the Automotive, Consumer, Networking, Wireless, IoT, Medical electronics and Foundry space. The company enables its customers to achieve their time-to-market window by delivering first pass silicon designs and engage with product engineering teams across the globe to design System on- Chip. Sankalp Semiconductor is based in Sunnyvale, California, with offices in USA, India, Canada, Germany and Malaysia. www.sankalpsemi.com
Practice:
Sankalp memory practice deals in memory compiler or instance development from specification to gds. Team with strong experience in development of low power, high performance, high density SRAM memories for 5nm to 180nm technology nodes. Team also has experience in developing flash memories. The project are done in T&M (time and material) or ownership/turnkey mode. The practice serves many leading MNCs involved in memory IP development.

Standard Cell Design

Job Description

Development of the standard cell library from scratch and support of existing libraries.
Circuit design: PPA tradeoff between different cell circuit architecture.
Experience in the field of Standard cell design, characterization, modelling and QA.
Design experience with deep sub-micron process
Should be well versed with standard EDA tools used for RC-extraction, SPICE simulators and schematic/layout editors.
Good Understanding of the views like lef, NLDM, CCS libs etc..
Understanding issues related to advanced nanometer technologies, IR, electro migration, SI, LOD, Proximity-effects etc..
Good automation skill using perl, tcl.
Good debugging and problem solving skills.
.
Job Requirements
Bachelors / Master Degree in E&E and E&C
Experience : 2 to 7 years
Strong communication and team work skills
Job Location : Bangalore

... More
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2-7 yrs. Delhi/NCR, Bengaluru/Bangalore

Practice: Sankalp memory practice deals in memory compiler or instance developm
Practice:

Sankalp memory practice deals in memory compiler or instance development from specification to gds.
Team with strong experience in development of low power, high performance, high density SRAM
memories for 5nm to 180nm technology nodes. Team also has experience in developing flash memories.
The project are done in T&M (time and material) or ownership/turnkey mode. The practice serves many
leading MNCs involved in memory IP development.

Job Description

Independent work execution
Experience working with circuit designers
Good experience in leaf cell/block level layouts
Good experience in memory compiler layouts
Good understanding and hands on experience using verification tools (Calibre) for
LVS and DRC
Experience in handling IR/EM related issues in memory layouts.
Awareness of second order effects
Experience of working in 16nm / 14nm / 10nm/ 7nm/ Finfet technology node is
preferred
Good communication skills and a team player

Job Requirements

Bachelors / Master Degree in E&E and E&C
Experience : 2 to 7 years
Strong communication and team work skills
Job Location : Bangalore / Noida
... More
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4-8 yrs. Bengaluru/Bangalore, Ahmedabad

Digital Verification team is working on IP verification and SoC verification pr
Digital Verification team is working on IP verification and SoC verification projects for our various tier 1 & tier2 global customers. This team provides verification solution for the entire verification cycle using industry standard methodology & tool. Candidate should be able to perform IP/SoC functional simulation, gate level simulation/low power simulation independently at Sankalp/Customer work location.


Job Description

4 to 8 years of verification experience
Defining verification plan
Creating test bench environment following methodology
Understanding technical requirements and writing the simple to complex test cases/scenarios, Simulate & Debug
Define verification metrics and tracking for verification sign-off
Customer interfacing for technical requirements
Guiding the junior engineers
Handle project team and execute independently

Roles & Responsibilities

Hands-on work experience in SoC & IP Level Verification
Experience in verifying SoC peripherals using ARM C and ARM processors
Good experience in C and Exposure to Assembly
Good AXI/AHB bus knowledge and ARM based SoC/Testbench exposure.
Hands-on experience in writing Test Plans, Coverage, Test cases/Scenarios
Hands-on in System Verilog (SV) and UVM based methodologies
Work experience in any of PCIe, MIPI,DDR, Ethernet, USB protocols
Formal connectivity verification at SoC level is a plus
Hands-on experience in Gate Level Simulation
Experience in Industry Standard Simulation tools
Experience of working at customer site
Experience of working with teams across geographies and managing project team
Experience of owning the technical deliverables
Good Communication Skill & Learning Attitude.

Job Requirements

Bachelors / Master Degree in E&E and E&C
Experience : 4 to 8 years
Strong communication and team work skills
Job Location : Bangalore / Ahmedabad

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